Gender

Male

Location

Kjeller, Norway

Birthday:

November 11

I am...

Engineer

My research field or area of interest innanotechnology

"Analytical Modeling of Low Leakage MGDG MOSFET and its Application to SRAM

Interest in...

• Analytical and Numerical Modeling for Multigate MOSFET (Square and Circular cross-section GAA, Double Gate, FinFET etc.) and their Circuit Applications, Nanoscale Memory Design, Ultra Low Power VLSI/ULSI Design and Technology, High Voltage Transistor Modeling.

Publication list

1. S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “Two Dimensional Analytical Potential Modeling of Nanoscale Fully Depleted Metal Gate Double Gate MOSFET,” Journal of Nanoelectronics and Optoelectronics (JNO), American Scientific Publishers (ASP), vol. 3, no. 3, pp. 297-306, 2008. 2. S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “Analytical Modeling of Inversion Charge Density for Nanoscale Dual Metal Gate (Hf/AlNx) and Midgap Symmetric Double Gate MOSFET” Journal of Nanoelectronics and Optoelectronics (JNO), American Scientific Publishers (ASP), vol. 4, no. 3, pp. 370-379, 2009. 3. S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “Modeling and Estimation of Drain Current for Dual Metal Gate (Hf/AlNx) and Midgap Symmetric Double Gate (SDG) MOSFET, Journal of Computational and Theoretical Nanoscience (JCTN), American Scientific Publishers (ASP), (Accepted). 4. S. K. Vishvakarma, V. Komal. Kumar, A. K. Saxena and S. Dasgupta, “Modeling and Estimation of Subthreshold Leakage Current for Dual Metal Gate (Hf/AlNx) Symmetric Double Gate (SDG) MOSFET” IEEE Trans. Electron Devices (Communicated). 5. S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “Analytical Modeling of Symmetric Double Gate (SDG) MOSFET using 1D Schrödinger-Poisson Equation Solution” Journal of Nanoelectronics and Optoelectronics (JNO), American Scientific Publishers (ASP), vol. 4, no. 3, pp. 353-361, 2009. 6. S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “Analytical Modeling of Potential and Drain Current for Symmetric Double Gate (SDG) MOSFET using Self Consistent Solution of 1-D Poisson's-Schrödinger Equations” Journal of Computational and Theoretical Nanoscience (JCTN), American Scientific Publishers (ASP), (Accepted). 7. S. K. Vishvakarma, V. Agarwal, B. Raj, A. K. Saxena and S. Dasgupta, “Two Dimensional Analytical Potential Modeling of Nanoscale Symmetric Double Gate (SDG) MOSFET with Ultra Thin Body (UTB)”, Journal of Computational and Theoretical Nanoscience (JCTN), American Scientific Publishers (ASP), vol.4, no. 6, pp. 1144–1148, 2007. 8. S. K. Vishvakarma, B. Raj, A. K. Saxena and S. Dasgupta, “Modeling of Inversion Charge Density in Nanoscale Symmetric Double Gate (SDG) MOSFET: An analytical Approach,” Journal of Nanoelectronics and Optoelectronics (JNO), American Scientific Publishers (ASP), vol. 2, no. 3, pp. 287-293, 2007. 9. S. K. Vishvakarma, B. Raj, A. K. Saxena, Rahul Singh, Chinmaya R. Panda and S. Dasgupta, “Evaluation of Threshold Voltage for 30 nm Symmetric Double Gate (SDG) MOSFET and it’s Variation with Process Parameters,” Journal of Computational and Theoretical Nanoscience (JCTN), American Scientific Publishers (ASP), vol. 5, no.4, pp. 619-626, 2008. 10. B. Raj, S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “A Compact Drain Current and Threshold Voltage Quantum Mechanical Analytical Modeling for FinFETs,” Journal of Nanoelectronics and Optoelectronics (JNO), American Scientific Publishers (ASP), vol. 3, no. 2, pp. 163-170, 2008. 11. B. Raj, S. K. Vishvakarma, A. K. Saxena and S. Dasgupta, “Analytical Modeling of Nanoscale Double Gate FinFET Device,” International Journal of Intelligent Electronics Systems, vol. 1. no. 1, pp. 66-71, 2007. 12. V. Komal Kumar, S. K. Vishvakarma, R. C. Joshi, A. K. Saxena and S. Dasgupta, “Latency Minimization of Nanoscale MGDG-MOSFET Based SRAM Cell Through Back Gate Bias for Low Leakage Operation: A Device/Circuit Co-Design Approach,” IEEE Trans. Electron Devices (Under Revision). 13. V. Komal, S. K. Vishvakarma, R. C. Joshi, A. K. Saxena and S. Dasgupta, “Small Signal Capacitance and Glitch Power estimation of Nanoscale MGDG-MOSFET Based Circuits: A Device/Circuit Co-design Approach” Journal of Nanoelectronics and Optoelectronics (JNO), American Scientific Publishers (ASP), (Communicated). 14. V. Komal, S. K. Vishvakarma, R. C. Joshi, A. K. Saxena and S. Dasgupta, “Nanoscale MGDG MOSFET based ULP SRAM cell design” Journal of Low Power Electronics, (Communicated

Researchgroup, Institute, University, School, Company name

,Unik-University Graduate Center, Kjeller, Norway

Researchgroup, Institute, Company, University, School webpage

https://sites.google.com/site/svishvakarma/

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