Gender

Female

Location

Jalandhar Punjab

Birthday:

September 10

I am...

Engineer, Teacher

My research field or area of interest innanotechnology

Low Power VLSI/Devices

Interest in...

MOSFET

Publication list

International journal  S L Tripathi, Ramanuj Mishra, R A Mishra, “High Fin Width MOSFET with GAA structure” international journal of VLSICS, vol 3,pp. 111-121,October-2012  S L Tripathi, Ramanuj Mishra,V Narendra, R A Mishra, “Optimization of pie-gate Bulk FinFET structure” in IJCA, vol 59, pp.34-39, December-2012  S L Tripathi, Ramanuj Mishra, R A Mishra, “Multi-gate MOSFET structures with high-k dielectric materials” in JED,vol 16, pp.1388-1394,Dec. 2012  S L Tripathi, R A Mishra, “Performance improvement of FinFET using spacer with high k dielectric” in JED, vol 17, pp.1447-1451, 2013  S L Tripathi, R A Mishra, “Design of 20 nm FinFET structure with round fin corners using side surface slope variation” in JED, vol 18, pp.1537-1542, 2013  S L Tripathi, Priti Gupta, Sandeep Mishra, R A Mishra, “Performance Improvement of Multi-Gate MOSFET with High-K Dielectric Materials” in IJICT, volume 3, no.6, 2013  S L Tripathi, Ramanuj Mishra, R A Mishra, “Optimization of high performance Bulk FinFET structure Independent of random dopent process variations” in Microelectronics and Solid state electronics, pp.29-38 May, 2013  Priti Gupta, S L Tripathi, Sandeep Mishra, “A novel Low leakage current and Power Consideration of 2 to 4 decoder” in IJAER as special issue which is having, Online ISSN 1087-1090, vol 7,2012.  SumanLata Tripathi, Ramanuj Mishra, Sandeep Mishra, Virendra Pratap Yadav & R.A.Mishra “Performance Comparison of Bulk FINFET with SOI FINFET in Nano-Scale Regime” IRNet Transactions on Electrical and Electronics Engineering, pp.114-118, 2012  Suman Lata Tripathi, Madhuraj Kumar, R. A. Mishra, “3-Dimensional channel potential model for doped symmetrical ultra-thin Quadruple Gate-All-Around MOSFET” Journal of Electron Devices, Vol. 21, pp. 1874-1880, May- 2015  Priti Gupta, Suman Lata Tripathi, Rajesh Mehra, “Power and Area Efficient Design of 6T Multiplexer using Transmission Gate Logic” communicated in International Journal of computer application in April-2015 International conference  S L Tripathi, Ramanuj Mishra, R A Mishra, “Characteristic comparison of connected DG FINFET, TG FINFET and Independent Gate FINFET on 32 nm technology” in IEEE conference by ICPCES, December,2012 at MNNIT, Allahabad  V Narendra,Sanjeev Rai, Suman Lata Tripathi, R A Mishra, A K Singh, “Performance evaluation of underlap double-gate and double-metal gate FinFET device for nanoscale applications” in Elsevier conference organized by ICECIT, 2012, Anantapur, Andhra Pradesh  S L Tripathi, Ramanuj Mishra,V Narendra, R A Mishra, “High performance Bulk FinFET with Bottom Spacer” in IEEE conference by CONECCT 17-19,January-2013 at IISC Bangalore.  S L Tripathi, Ramanuj Mishra, R A Mishra, “ Design of Bulk FinFET with Improved Performance over SOI FINFET” in Proceedings of conference ICEEE organized by ICICT-2012, pp.409-412,Delhi  Pragati Singh, S.L.Tripathi, S.P singh, “Triple Band Microstrip Patch Antenna with improved gain” in IEEE conference, 11-12, February-2016, at KNIT Sultanpur. International conference papers communicated  Priti Gupta, Suman Lata Tripathi, “Low Power Design of Bulk Driven Operational Transconductance Amplifier”accepted in IEEE conference, Devic2017. National conference  S L Tripathi, Shailndra Sinha, Ashutosh Mishra, “Two dimensional threshold voltage model for doped symmetric DG MOSFET in subthreshold region of operation” in proceedings of national conference of NCETVLSI, MIET,Meerat, pp.94-99, 2011  S L Tripathi, Ashutosh Mishra, “Analysis of leakage reduction and delay characteristics in dynamic circuit” in proceedings of national conference of NCETVLSI, MIET, Meerat, pp.14-28, 2011 ________________________________________  Research area: ________________________________________  “Design and Optimization of Multi-Gate MOS devices” under Supervision of Mr. R.A. Mishra, Associate Professor in Department of electronics and communication, MNNIT, Allahabad.  Also guiding M.Tech students in “Low Power VLSI Design” at Kashi IT, Varanasi  Currently working on Low frequency Noise model of MOSFET

Researchgroup, Institute, University, School, Company name

Lovely Professional University, Punjab,

Researchgroup, Institute, Company, University, School webpage

https://researchgate,Lovely Professional university

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