SEM Image and Cross Sectioning by CVTC student Rob Haveman
This is one of the major projects for second semester nanoscience students and it is also a useful technique to know how to do since many manufacturers have a need for cross sections. This is a common procedure performed by people who use the electron microscope. I started doing this procedure my second semester of teaching nanoscience because not only because it was a useful skill but because it utilized the equipment I had available to me and gave the students a chance to make use of a variety of equipment. It also matches the semiconductor fabrication curriculum this semester fairly well and helps the students to get more time on the SEM, EDS and OM.
The procedure is for the students to obtain a computer chip and prepare it for SEM analysis by making a cross section of the chip. To obtain a cross section the chip is typically mounted in an epoxy or compression mounting material. It is then polished to a scratch free mirror like surface using decreasing polishing grids. After polishing an optical microscope image of the computer chip circuitry may be obtained. This circuitry is very difficult to image well in an optical microscope. The chip is then stained using Wright Etch to highlight the different materials. The chip is sputter coated and loaded into the SEM.
The students are required to obtain an SEM image, perform EDS analysis to determine the composition of the layers of the chip and measure the thicknesses of the different layers of the chip. In a more advanced class they could also be asked to determine the process steps needed to create the structures observed. The image above shows one of the results from this years class.
Computer chips can be obtained from nearly any old electronic devices such as telephones, VCR or DVD players, electronic toys, remote controls, computers etc. Older, larger, thicker chips tend to work better. The older chips are nicer because they have larger metallization. The larger chips are nicer because it is easier to hit the silicon chip inside the package without polishing through it completely. The thin surface mount chips are difficult to handle and process. If you can get some unpackaged silicon that will be much easier to process.
The chips usually must be removed from the circuit board. I use pliers, knife, wire cutters etc. to remove the chips from the board. If you want to you could try desoldering. Next the packaged device must be cut in half. I try to cut about 1/3 of the end off then switch to sand paper. Once the silicon is visible you can go to a finer grade of sand paper. The silicon is often mounted on a copper heat sink using silver paste. The actual metallization will be found on the silicon chip opposite the copper backing plate. You may not be able to see it until you get to a very fine polish and use a high magnification.
One of the most common problems I see when the students start polishing the chips is a crack developing near the top surface of the silicon that continues to propagate and disrupt the surface. I think this may be due to using a rough sand paper. After the sand paper we mount the sample using a compression mounting system. This embeds the chip in a polymer disk. You can also use epoxy to mount the sample. I had trouble with the epoxy curing properly so I have switched to the compression mount which seems to work reliably in a shorter time. The sample should be mounted with the silicon directly on the bottom so that it can be polished after mounting.
Next we go to a polishing/lapping wheel. We are currently using diamond embedded polishing disks available from Allied High Tech:
Buehler also has a number of polishing products. Buehler also has a number of tech notes for preparing different types of samples. We go through 30 micron, 15, 9, 6, 3, 1, .5, .1 then switch to a .05 alumina slurry on a felt pad. After each step the student needs to inspect the chip on an optical microscope and clean the chip so that particles from the larger pads do not contaminate the smaller disks. The students need to clean debris from the polishing disks with a Q-tip occaisionally. This disks are expensive and need to be taken care of. After each disks the student should rotate the chip by 90 degrees and polish until no scratches from the perpendicular direction remain. Another problem with this lab is that there is often congestion at the polishing wheel. That is why I split the class and have some of them work on the circuit board project at the same time.
By 6-3 microns you will probably start to see some devices appearing near the top of the chip. There may be some smeared metal appearing up there. I have heard that you can reduce metal smearing by slowly dropping some HCl on the pad as you polish. I usually just let the Wright etch take care of everything at the end. The Wright etch is carcinogenic and includes HF which has some special hazards associated with it which you need to be aware of if you use it. The recipe can be found online. It works really well to highlight the features on the chip. You only need to put about one drop of Wright etch on the polished silicon for 2-3 seconds. The chip shown above went for about 10-15 seconds which is too long. I do not let the second semester students handle the Wright etch.
After the Wright etch the sample will typically need to be sputter coated. Afterwards the sample is loaded into the SEM for imaging measurement and EDS analysis.