Researchers in electrical and computer engineering at University of California, Santa Barbara have introduced and modeled an integrated circuit design scheme in which transistors and interconnects are monolithically patterned seamlessly on a sheet of graphene, a 2-dimensional plane of carbon atoms. The demonstration offers possibilities for ultra energy-efficient, flexible, and transparent electronics. The top schematic is a monolayer graphene sheet. The center schematic displays etched narrow/wide ribbons acting as semiconductor/metal. The bottom schematic is an all-graphene circuit after deposition and patterning of metal and gate dielectric. Credit: UCSB Nanoelectronics Research Lab Bulk materials commonly used to make CMOS transitors and interconnects pose fundamental challenges in continuous shrinking of their feature-sizes and suffer from increasing “contact resistance” between them, both of which lead to degrading performance and rising energy consumption. Graphene-based transistors and interconnects are a promising nanoscale technology that could potentially address issues of traditional silicon-based transistors and metal interconnects. “In addition to its atomically thin and pristine surfaces, graphene has a tunable band gap, which can be adjusted by lithographic sketching of patterns—narrow graphene ribbons can be made semiconducting while wider ribbons are metallic. Hence, contiguous graphene ribbons can be envisioned from the same starting material to design both active and passive devices

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