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Ritesh Gupta
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  • Gurgaon, Haryana
  • India
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Ritesh Gupta replied to TINC's discussion Looking for PhD or Postdoc position
"I Dr. Ritesh Gupta have completed my PhD in electronics from the University of Delhi in September 2003. The subject of my dissertation is modelling, simulation, and optimization of field effect transistors and specifically the major High electron…"
Sep 21, 2011

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Profile Information

I am...
Student
My research field or area of interest innanotechnology
Microelectronics devices, semiconductor devices, HEMT, MOSFET, MESFET, modeling, simulation
Interest in...
fabrication,
Publication list
Year of publication 2010
1. “Microwave performance Enhancement in Double and Single Gate HEMT with Channel Thickness Variation”.
Paper published in “Superlattices and Microstructures Vol. 47, pp. 779-794, 2010".
2. “Metal Insulator Gate Geometric HEMT: Novel Attribute and Design Consideration for High Speed Analog Applications”.
Paper published in “Journal of Semiconductor Science and Technology Vol. 10, no.1, pp. 66-77 March 2010”.
Year of publication 2009
3. “A Study of Technological Defects and Carrier Quantization Effects”.
Paper presented at “ISMOT-2009”.
4. “Dynamic Performance of Graded Channel DG FD SOI n-MOSFET for Minimizing the Gate Misalignment Effect”.
Paper published in “Microelectronics Reliability Vol. 49, pp. 699-706, July 2009”.
5. “Dual Material Double Gate SOI n-MOSFET: Gate Misalignment Analysis”.
Paper published in “IEEE Trans Electron Devices Vol. 56, no.6, pp. 1284-1291, 2009”.
6. “T-gate Geometric (Solution for Sub-micrometer Gate Length) HEMT: Physical Analysis, Modeling and Implementation as Parasitic Elements and its usage as Dual Gate for Variable Gain Amplifiers”.
Paper published in “Superlattices and Microstructures Vol. 45, pp. 105-116, 2009”.
Year of publication 2008
7. “Comparative Sub-Threshold Analysis for Channel Thickness Variation on Sub-100 nm Double Gate with Single-Gate HEMT”.
Presented at “2008 International Conference on Recent Advancements in Microwave Theory and Applications in 2008”.
8. “Graded Channel Architecture: the Solution for Misaligned DG SOI n-MOSFETs”.
Paper published in “Semiconductor Science and Technology Vol. 23, no.7, 075041 (14pp) July 2008”.
Year of publication 2007
9. “Short Channel Analytical Model for High Electron Mobility Transistor to obtain High Cut-off Frequency maintaining the reliability of the device”.
Paper published in “Journal of Semiconductor Science and Technology Vol. 7, no.2, pp. 120-131 June 2007”.
Year of publication 2006
10. “An Analytical Model for Various Gate Insulator Geometries (N, L,  and T-gate) of SOI SIC MESFET”.
Paper presented at “CODEC-06, Hyatt Regency, Kolkata, India (Dec 18-20, 2006)”.
11. “An Analytical model for Metal Insulator Semiconductor High Electron Mobility Transistor (MISHEMT) for its higher frequency and high power applications”.
Paper published in “Journal of Semiconductor Science and Technology Vol. 6, no.3, pp. 189-198 September 2006”.
12. “An Analytical model for Discretized Doped InAlAs/InGaAs Heterojunction HEMT for higher Cut-off frequency and Reliability”.
Paper published in “Microelectronic Journal Vol.37/9 pp 919-929 2006”.
13. “A Semi Empirical Approach for Submicron GaN MESFET Using an Accurate Velocity Field Relationship for High Power Applications”.
Paper published in “Microelectronic Journal Vol. 37/7 pp 620-626 2006”.
Year of publication 2005
14. “A Physics Based Analytical Model for Buried p-layer Non-Self Aligned SiC MESFET for the Saturation Region”.
Paper published in “Solid State Electronics Vol. 49, no.7, pp. 1206-1212, 2005”.
15. “Analytical non-linear Charge Control Model for InAlAs/InGaAs/InAlAs Double Heterostructure High Electron Mobility Transistor (DH-HEMT)”
Paper published in “Solid State Electronics Vol. 49, no.2, pp. 167-174, 2005”.
16. “Analytical Model for high temperature performance of Non-Self Aligned SiC MESFET”.
Paper published in “Indian Journal of Pure and Applied Physics, Vol.43 pp. 697-704, September 2005”.
Year of publication 2004
17. “Analytical Model for Non-Self Aligned Buried P-layer SiC MESFET".
Presented in “IEEE Lester Eastman Conference (LEC) on high performance devices, Troy New York, August 2-6, 2004”.
18. “Analytical Model for Non-Self Aligned Buried P-layer SiC MESFET”.
Paper published in “International Journal of High Speed Electronics and Systems, Vol. 14, no.3, pp. 897-905, 2004”.
19. “Optimization of InAlAs/InGaAs HEMT Performance for Microwave Frequency Applications and Reliability”.
Paper published in “Journal of Semiconductor Science and Technology Vol. 4, no.3, pp. 230-239 September 2004”.
20. “A New simplified Analytical Short-channel Threshold Voltage Model for InAlAs/InGaAs Hetero-structure InP based Pulsed Doped HEMT”.
Paper published in “Solid State Electronics Vol. 48, no.3, pp. 437-443, 2004”.
Year of publication 2003
21. Optimization of InAlAs/InGaAs hetero-structure, InP based HEMT for its Microwave Frequency Applications”.
Paper published in “Proceeding of SPIE Vol. 5445, pp. 466 – 471, 2003”.
22. “Modeling Characterization and Optimization of Tri – Step doped InAlAs/InGaAs Hetero-structure, InP based HEMT for Microwave Frequency Applications”.
Paper published in “Indian Journal of Pure and Applied Physics Vol.41 pp. 223-231, March 2003”.
23. “Optimization of InAlAs/InGaAs hetero-structure, InP based HEMT for its Microwave Frequency Applications”.
Presented in “ISMOT-03, August 11-15, 2003”.
24. “A New Depletion Dependent Analytical Model for Sheet carrier density of InAlAs/InGaAs Hetero-structure InP based HEMT”.
Paper published in “Solid State Electronics Vol. 47, no.1, pp. 33-38, 2003”.
25. “Depletion Dependent Analytical Model for InAlAs/InGaAs/InP HEMT”.
Presented in “National Symposium on Advances in Microwaves and Lighwaves (NSML-2003) October 13-14, 2003, Pp 52-55”.
Year of publication 2002
26. “Model for Optically Biased Short Channel GaAs MESFET”.
Paper published in “Microwave and Optical Technology Letters Vol. 32, No. 2, pp. 138 – 142, January 20 2002”.
27. “An Analytical Parasitic Resistance Dependent Id-Vd Model for planer doped InAlAs/InGaAs/InP HEMT using charge control analysis”.
Paper published in “Microelectronics Engineering, Vol. 60, no. 3 – 4, pp. 323-337, 2002”.
28. “An Analytical Two-dimensional Model for Pulsed Doped InP-based Lattice-matched HEMTs for High Frequency Applications”.
Paper published in “Indian Journal of Pure and Applied Physics Vol. 40, pp. 342 – 349, 2002”.
29. “An Accurate model for planar Doped InAlAs/InGaAs/InP MODFETs for Microwave Circuit Applications”.
Paper presented at “IWPSD, 2002”.
Year of publication 2001
30. “An Analytical Model for I-V Characteristics of Optically Controlled Surrounding/ Cylindrical Gate (SGT) MOSFET”.
Paper presented at “ELECTRO-2001 January 4-6, 2001”.
31. “An Accurate Charge Control Model for InAlAs/InGaAs/InP Modulation Doped Field Effect Transistors”,
Paper presented at “ELECTRO-2001 January 4-6, 2001”.
Year of publication 2000
32. “Analytical Model for threshold voltage adjustment by gate material workfunction control in double gate SOI MOSFETs”.
Presented in “National Seminar on VLSI: system design and technology, IIT Bombay, India, 2000”.
Researchgroup, Institute, University, School, Company name
SDRL, Deparment of Electronics, Delhi University
Researchgroup, Institute, Company, University, School webpage
http://www.du.ac.in/
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